1. Field of the Invention
The following invention relates to information handling systems, and more particularly to information handling systems including multiphase clocks.
2. Prior Art
U.S. Pat. No. 4,899,066, entitled "OR-Type CMOS Logic Circuit with Fast Precharging", teaches a complimentary metal oxide semiconductor (CMOS) logic circuit including a signal line OR connecting a plurality of MOS transistors which are turned on and off by a plurality of decoder outputs. The signal line is divided by a MOS-FET in two portions, including a portion on an output side provided with an inverter and an OR connected transistor side, so that respective portions of the signal line as divided are precharged by separate precharging MOS transistors.
While the circuit of the '066 patent has some superficial similarities to embodiments of Applicants' invention, the '066 patent is a point of departure since it does not include essential elements of Applicants' invention.
U.S. Pat. No. 4,700,086, entitled "Consistent Precharge Circuit for Cascode Voltage Switch Logic", teaches a precharge circuit for a cascode voltage switch in which, at the beginning of the precharge phase, the output state is memorized and the output is isolated from the precharging points. Both the positive and negative ends of the discharge paths are precharged with the gates of the switches in all paths held in their memorized states.
Although the '086 patent teaches a CMOS domino circuit having feedback on an output inverter and a series gate between the logic circuit and the inverter, the '086 patent does not include essential elements of Applicants' invention.
U.S. Pat. No. 5,065,048, entitled "Semiconductor Logic Circuit with Noise Suppression Circuit", teaches a dynamic semiconductor logic circuit including an MOS-FET logic section for effecting a high speed logic information in response to input logic signal after precharging of an output mode an internal nodes the logic section, a CMOS output buffer section for outputting a result of the logic operation, and a noise suppression section for preventing erroneous operations without sacrificing the high speed operation characteristic.
Although there are some similarities between the '048 patents circuit and that of the present invention, essential elements of the present invention are not taught nor suggested in the '048 patent.
An article entitled "Design Performance Tradeoffs in CMOS-Domino Logic", by V. G. Oklobdzija and R. K. Montoya, published in the IEEE Journal of Solid State Circuits, Vol SC-21 No. 2, April 1986 at p. 304, provides a baseline prior art domino circuit but does not include the inventive aspects of the present invention as described and claimed herein.
Another example of early domino logic circuits is an article entitled "Design Performance Tradeoffs in CMOS-Domino Logic", by V. G. Oklobdzija and R. K. Montoya, published in the IEEE 1985 Custom Integrated Circuits Conference Proceedings, at p. 334, which as above shows some early domino logic, but does not teach nor suggest essential elements of the present invention as shown and claimed herein.
An article entitled "An Improvement for Domino CMOS Logic", by C. Zhang, published in Computer and Electrical Engineering, Vol. 13, No. 1, pp. 53-59 in 1987, shows another improvement in domino CMOS logic, but does not teach nor suggest essential elements of the present invention as claimed herein.
U.S. Pat. No. 5,041,742, entitled "Structured Scan Path Circuit for Incorporating Domino Logic", teaches a design for a structured scan path circuit incorporating domino logic circuitry. Scan path circuit allows the rapid evaluation of a predetermined logic function, while allowing the use of automatic test pattern generation programs. Each function input signal has its own latch, the equivalent to the master latch in a standard scan flip-flop.
The structure of the circuit of the '742 patent is more complex and requires many latches and other elements which are not required by the present invention as claimed herein.
U.S. Pat. No. 4,849,658, entitled "Dynamic Logic Circuit Including Bipolar Transistors and Field Effect Transistors", teaches a dynamic logic circuit arranged to realize high speed operation. The circuit includes bipolar transistors coupled to CMOS logic including a precharging device coupled between a second potential and the output of the dynamic logic circuit to precharge the output according to at least one clock signal which periodically changes its state.
The '658 patent while teaching a simple CMOS gate circuit with precharging, does not teach not suggest essential elements of the present invention as claimed herein.
U.S. Pat. No. 4,780,626, entitled "Domino Type MOS Logic Gate Having a MOS Subnetwork", teaches a logic MOS gate of the domino type having a precharging transistor, a validation transistor and logic transistors.
The '626 patent teaching relates to a logic gate and does not include essential elements of the present invention as claimed herein.